• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In an SOI wafer manufacturing method, an oxide film is formed on the surface of at least one of two silicon wafers; Hydrogen ions or rare gas ions are implanted into the top surface of one of the two silicon wafers to form a microbubble layer (enclosed layer) in the wafer; The ion-implanted silicon wafer is superimposed on the other silicon wafer such that the ion-implanted surface closely contacts the surface of the other silicon wafer through the oxide film; In order to form a thin film, an SOI wafer is obtained by performing a heat treatment to peel off a portion of the ion-implanted wafer while using the microbubble layer as the release surface. In this method, the defect layer on the exfoliated surface of the SOI wafer thus obtained is removed to a depth of 200 nm or more through gas phase etching, and then mirror polishing is performed. Thus, the obtained SOI wafer has a very low level of defects and a high thickness uniformity.
    公开号:KR19990030065A
    申请号:KR1019980039446
    申请日:1998-09-23
    公开日:1999-04-26
    发明作者:히로지 아가；키요시 미타니；유끼오 이나즈끼
    申请人:와다 다다시；신에쯔 한도타이 컴파니 리미티드；
    IPC主号:
    专利说明:

    SOI wafer manufacturing method and SOI wafer manufactured by the method
    The present invention provides a silicon on SOI fabricated according to a method (smart-cut method) of obtaining an SOI wafer by bonding an ion-implanted wafer to another wafer and peeling a portion of the ion-implanted wafer. to a surface treatment of a wafer having an insulator) structure.
    Conventionally, two methods are widely known as a method of manufacturing a wafer having an SOI structure. One method is separation by implanted oxygen (SIMOX), in which oxygen ions are implanted in high concentration into a silicon single crystal and then heat treated at high temperature to form an oxide film. Another method is to join two mirror-polished silicon wafers together without using an adhesive and then thin one of the wafers.
    In the SIMOX method, the thickness of the SOI layer serving as the device active region can be determined and controlled by adjusting the accelerating voltage during oxygen ion implantation. Thus, the SIMOX method has the advantage of easily forming a thin SOI layer with high thickness uniformity (hereinafter referred to as thickness uniformity). However, the SIMOX method has many problems with regard to the reliability of the buried oxide film, the crystallinity of the SOI layer, the need for heat treatment at a temperature of 1300 ° C or higher.
    On the other hand, in the wafer bonding method, an oxide film is formed on at least one of two mirror-polished silicon single crystal wafers, bonded together without using an adhesive, and then heat treated (typically at 1100 to 1200 ° C.) to strengthen the bonding; One of the wafers is then ground or wet etched to thin the wafer, and then the surface is mirror-polished to form an SOI layer. Therefore, the buried oxide film is highly reliable and the crystallinity of the SOI layer is good. However, since the thin film is formed by a mechanical processing method, there is a limit in the thickness and uniformity of the resulting SOI layer.
    In the wafer bonding method, not only the silicon wafers are bonded together, but also silicon wafers can be directly bonded to an insulating wafer such as SiO 2 , SiC, Al 2 O 3 , to form an SOI layer.
    Recently, the public's attention has focused on new SOI wafer fabrication methods; That is, the so-called smart-cut method of obtaining an SOI wafer by bonding an ion-implanted wafer to another wafer and peeling off a portion of the ion-implanted wafer. In this method, an oxide film is formed on the surface of at least one of two silicon wafers; Implanting hydrogen ions or rare gas ions into the surface of one of the two silicon wafers to form a fine bubble layer (encapsulation layer) in the wafer; The ion implanted silicon wafer is superimposed on the other silicon wafer such that the ion-implanted surface closely contacts the other silicon wafer through the oxide film; In order to form a thin film, heat treatment is performed to peel off a portion of the ion-implanted wafer while using the fine bubble layer as the peeling surface; The heat treatment is performed again to firmly bond the thin film and the other wafer to obtain an SOI wafer (see Japanese Patent Laid-Open No. 5-211128). In addition, in this method, since the surface formed as a result of the peeling (hereinafter referred to as a delaminated surface) has a mirrored surface, the SOI wafer is relatively easily obtained with a high thickness uniformity of the SOI layer.
    In the final step of the method, a very small amount of stock removal mirror polishing (70-100 nm), called touch polishing, is performed directly to reduce surface roughness and remove the defect layer.
    However, when evaluating SOI layers not yet touch polished according to the four-step Secco-etching disclosed by H. Gassel et al. (J. Electrochem. Soc., 140, pp 1713, 1993), The thickness was found to be about 200 nm. The defect layer is thought to be due to deformation and damage generated during hydrogen ion implantation.
    This defect layer can be removed if the amount of stock removed by touch polishing is increased to 200 nm or more. In this case, however, the uniformity of stock removal over the entire wafer surface is lowered, resulting in an increase in the thickness change of the SOI layer. In particular, when the thickness of the SOI layer is small, increasing the thickness change has a large adverse effect on the semiconductor device, resulting in a loss of product value.
    The present invention has been made in view of the above problems. It is an object of the present invention to reliably remove a layer of crystal defects deep in the exfoliated surface obtained by a method of obtaining an SOI wafer by combining an ion-implanted wafer with another wafer and exfoliating a portion of the ion-implanted wafer, It is to provide a method for producing SOI wafers with good thickness uniformity and high crystallinity relatively easily at relatively low cost.
    1 is a flow diagram illustrating an example of a method of fabricating an SOI-wafer to obtain an SOI wafer by bonding an ion-implanted wafer to another wafer and peeling off a portion of the ion-implanted wafer.
    2A and 2B are schematic diagrams illustrating a vapor phase etching method performed by a plasma assisted chemical etching (PACE) method, in which FIG. 2A is a perspective view and FIG. 2B is a sectional view.
    FIG. 3 is a graph showing the relationship between the crystal defect layer and the defect pit density on the exfoliated surface of the SOI wafer manufactured by the method shown in FIG.
    In order to achieve the above object, the present invention provides an oxide film on at least one surface of two silicon wafers; Implanting hydrogen ions or rare gas ions into the top surface of one of the two silicon wafers to form a microbubble layer (encapsulation layer) in the wafer; Superimposing the ion-implanted silicon wafer on the other silicon wafer such that the ion-implanted surface closely contacts the surface of the other silicon wafer through the oxide film; In order to form a thin film, an SOI wafer is obtained by performing a heat treatment to peel a part of the ion-implanted wafer while using a microbubble layer as the peeling surface, and a defect layer on the peeled surface of the SOI wafer thus obtained is obtained in the gas phase. A method of manufacturing an SOI wafer, which is removed by etching, is provided.
    As described above, when fabricating an SOI wafer according to a method in which an ion-implanted wafer is bonded to another wafer and a portion of the ion-implanted wafer is peeled off to obtain an SOI wafer, a thick crystal defect layer is formed on the peeled surface of the SOI wafer. Is formed. Vapor-phase etching is effective in removing such defect layers. Through vapor phase etching, even when a large amount of stock is removed, the crystal defect layer can be removed while making the thickness of the SOI layer uniform.
    The invention also injects hydrogen ions or rare gas ions into the top surface of the silicon wafer to form a microbubble layer (encapsulation layer) in the wafer; Superimposing the ion-implanted wafer on the insulating wafer such that the ion-implanted surface is in close contact with the insulating wafer; In order to form a thin film, an SOI wafer is obtained by performing a heat treatment to peel a part of the ion implanted wafer while using a fine bubble layer as a peel plane, and the defect layer on the peeled surface of the SOI wafer thus obtained is vapor phase etching. It provides a method of manufacturing a SOI wafer to remove through.
    As described above, a method of obtaining an SOI wafer by bonding an ion-implanted wafer to another wafer and peeling a portion of the ion-implanted wafer is not only when the silicon wafers are bonded together, but also when the silicon wafers are bonded to SiO 2 ,. It is also applicable to the case where it is directly bonded to an insulator wafer such as SiC and Al 2 O 3 .
    Preferably, the defect layer is removed to a depth of 200 nm or more by vapor phase etching.
    If the bonding layer is removed to a depth of 200 nm or more, the defect layer can be reliably removed. Therefore, it becomes possible to manufacture an SOI wafer in which the SOI layer has a uniform thickness.
    Preferably, the surface treated by vapor phase etching is then mirror polished.
    Although the crystal defect layer is reliably removed through the surface treatment using vapor phase etching, a new surface roughness called HAZE is generated during the surface treatment. However, this surface roughness can be removed, if necessary, via mirror polishing, or more preferably touch polishing.
    The method of the present invention can remove a crystal defect layer on an exfoliated surface of an SOI wafer manufactured by joining an ion-implanted wafer to another wafer and peeling a portion of the ion implanted wafer to obtain an SOI wafer. Make sure Thus, it is possible to obtain an SOI wafer having an SOI layer with very low levels of defects and good thickness uniformity.
    As described above, in the present invention, crystal defects on the surface of the SOI layer of the SOI wafer manufactured by the method of obtaining the SOI wafer by bonding the ion-implanted wafer to another wafer and peeling off a portion of the ion-implanted wafer. Vapor phase etching is performed to remove the layer. Thus, the film thickness of the SOI layer can be made uniform. In addition, when mirror polishing is additionally performed to reduce the surface roughness of the SOI layer, SOI wafers with uniform thickness, reduced surface roughness, very low levels of defects, and high crystalline SOI layers are relatively easy and inexpensive. It becomes possible to manufacture.
    Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to this.
    The technique for the present invention focuses on the case where two silicon wafers are joined together.
    1 obtains an SOI wafer by bonding an ion-implanted wafer to another wafer and peeling off a portion of the ion-implanted wafer, which additionally includes a vapor-phase etching step and a touch polishing step. It is a process chart which shows the manufacturing method of the SOI-wafer including the polishing step). This method can be carried out in two different ways (method A and method B) with different sequence of process steps. First, method A is described.
    In step 1 of method A, two mirror-polished silicon wafers 20 and 21 are made to meet device specifications.
    In step 2 of Method A, at least one of the wafers (in this case wafer 20) is thermally oxidized to form an oxide film 30 having a thickness of about 0.1-2.0 μm on their surface.
    In step 3 of method A, a wafer is prepared by injecting hydrogen or rare gas ions into one surface of another silicon wafer 21 to extend the microbubble layer (encapsulation layer) 40 parallel to the surface at a position corresponding to the average depth of ion implantation. To form. The injection temperature is preferably 25 to 450 ° C.
    In step 4 of Method A, the ion-implanted wafer 21 is superimposed on another wafer 20 such that the ion-implanted surface is in close contact with the oxide film 30 of the wafer 20. When the surfaces of the two wafers are in close contact with each other at room temperature under a clean atmosphere, the wafers adhere to each other without using an adhesive or the like.
    In step 5, a peeling heat treatment is performed in which the upper wafer portion 28 is peeled from the lower SOI wafer 10 (comprised of the SOI layer 25, the buried oxide layer 26, and the substrate wafer 27) while using the encapsulation layer 40 as the peeling surface. That is, when the heat treatment is performed at a temperature of about 500 ° C. or more under an inert gas atmosphere, crystal rearrangement and bubble aggregation occur to exfoliate the upper wafer portion from the lower SOI wafer. After that, the exfoliated upper wafer portion 28 is removed.
    In step 6, since the bonding force imparted in step 4 is too low for the device process, heat treatment is applied to the wafers that are brought into close contact with each other in step 4 above to increase the bonding force to a sufficient level. Preferably, this heat treatment is carried out in an inert gas atmosphere at 1050 to 1200 ° C. for 30 minutes to 2 hours.
    Alternatively, the heat treatment for peeling in step 5 and the heat treatment for bonding in step 6 may be performed continuously so that the upper wafer portion 28 peeled off in step 5 is not removed from the lower SOI wafer. Alternatively, a single heat treatment may be performed for steps 5 and 6.
    In step 7, vapor phase etching removes the crystal defect layer of the exfoliation surface 50, which is the surface of the SOI layer 25, and makes the thickness of the SOI layer 25 uniform. This step preferably uses the PACE method where RF plasma 16 is locally generated in cavity 12 to perform vapor phase etching, as shown in FIGS. 2A and 2B. The order of the above steps 5-6-7 can be changed to 5-7-6.
    The PACE method is one form of dry etching. First, the thickness distribution of the SOI layer of the SOI wafer 10 is measured. When the cavity 12 is moved on the SOI wafer 10, the moving speed of the cavity 12 is adjusted according to the thickness distribution, so that the time during which each portion is exposed to the plasma 16 is adjusted. As a result, since the amount of etching removal on the surface is controlled, the thickness of the SOI filling of the SOI wafer 10 is made uniform while the surface bonding layer of the SOI layer is removed. Plasma 16 is locally generated in cavity 12 by applying an RF voltage from RF power source 15 to electrodes 13 and 14 located above and below SOI wafer 10. The cavity 12 is supported to be free to move on the SOI wafer 10.
    The present invention not only uses the PACE method of removing the crystal defect layer of the exfoliation surface 50, which is the surface of the SOI layer 25, and performs the vapor phase etching step to make the thickness of the SOI layer 25 uniform, as well as the various conditions of the PACE method. It was accomplished by careful decision.
    In particular, the gas phase etching is preferably performed to a depth of 200 nm or more. Therefore, surface defects, surface damages, and the like induced by ion implantation can be reliably removed.
    It was confirmed that the gas phase etching can remove the crystal defect layer and improve the thickness uniformity even when a large amount of stock is removed, without reducing the thickness uniformity of the SOI layer.
    Step 8 is a touch polishing step to remove surface haze generated during the vapor phase etching in step 7. If necessary, the gas phase-etched surface is mirror-polished to 5-15 nm, preferably about 10 nm.
    By the above method, a high quality SOI wafer 10 having an SOI layer 25 having a high thickness uniformity is produced.
    Hereinafter, the SOI wafer manufacturing method by the method B is described. In step 1 of method B, two mirror-polished silicon wafers 22 and 23 are fabricated that meet the device specifications. In step 2 of Method B, at least one of the wafers (in this case wafer 23) is thermally oxidized to form an oxide film 31 having a thickness of about 0.1-2.0 μm on their surface. In step 3 of Method B, hydrogen or rare gas ions are implanted into the oxide film 31 of the wafer 23 to form a microbubble layer 41 (inclusion layer) 41 extending parallel to the surface at a position corresponding to the average depth of ion implantation in the wafer. do. The injection temperature is preferably 25 to 450 ° C. In step 4 of Method B, the ion-implanted wafer 23 is overlaid on the silicon wafer 22 such that the ion-implanted surface of the wafer 23 or the oxide film 31 is in close contact with the surface of the silicon wafer 22. When the surfaces of the two wafers are in contact with each other at room temperature under a clean atmosphere, the wafers are adhered to each other without using an adhesive or the like.
    Subsequently, in steps 5 to 8, by performing the same processing methods as in method A, an SOI wafer having an SOI layer having a uniform thickness without crystal bonding is obtained.
    Example
    Next, an Example demonstrates this invention. However, the present invention is not limited to this.
    (Example)
    28 mirror-polished silicon wafers (conductive type: p-type; resistivity: 10 Ω · cm) having a diameter of 150 mm were prepared. These wafers were processed by steps 1 to 6 of Method B shown in FIG. 1 to obtain 14 SOI wafers with an SOI layer having a thickness of 870 nm. The main process conditions used in this method are:
    a) thickness of buried oxide film: 400 nm;
    b) hydrogen implantation conditions: H + ions, implantation energy: 150 keV, implantation volume: 8 x 10 16 / cm 2 ; c) peeling heat treatment condition: 30 minutes at 500 ° C. under N 2 gas atmosphere; And
    d) Bonding heat treatment condition: 2 hours at 1100 ° C. under N 2 gas atmosphere.
    Of the SOI wafers manufactured in this manner, 12 SOI wafers were vapor phase etched at a time according to the PACE method so that the SOI layer was etched to a depth of 90 nm, 140 nm, 190 nm, 290 nm, 490 nm or 680 nm (six types). It was. Subsequently, selective etching was performed according to the four-step Secco-etching to measure the density of defect pits (hereinafter referred to as defect pit density) at the surface of each SOI layer. The measurement result is shown in FIG. In FIG. 3, the horizontal axis represents the stock removal thickness of the SOI layer, and the vertical axis represents the defect pit density. 3 shows the average value of two wafers with SOI layers removed to the same depth. For comparison, two remaining wafers without gas phase etching were evaluated for their defect pit density according to the four step Secco-etching method. The evaluation results are also shown in FIG. 3.
    As clearly shown in Fig. 3, as the stock removal amount of the SOI layer increases to about 200 nm, the density of the defect pits decreases rapidly; However, if the stock removal amount of the SOI layer is increased to 200 nm or more, the density does not actually change and remains at a low level. Thus, when the defect layer is etched to a depth of at least 200 nm, an SOI wafer with an SOI layer having extremely low levels of defects is obtained.
    The present invention is not limited to the above embodiment. The above embodiments are merely examples, and those having the same structure as those described in the claims and providing similar actions and effects are included in the scope of the present invention.
    For example, the above descriptions focused on the case where two silicon wafers were combined to obtain an SOI wafer. However, the present invention is not limited to the above embodiment. For example, the present invention relates to a case in which a silicon wafer is bonded to an insulator wafer; When ion-implanted wafers are bonded to them; And part of the ion-implanted wafer to be peeled off to obtain an SOI wafer.
    As described above, according to the method of the present invention, it is possible to provide an SOI wafer having a high thickness uniformity, high crystallinity, and an extremely low SOI layer having an extremely low level of defects.
    权利要求:
    Claims (16)
    [1" claim-type="Currently amended] Forming an oxide film on a surface of at least one of the two silicon wafers;
    Implanting hydrogen ions or rare gas ions into the top surface of one of the two silicon wafers to form a microbubble layer (encapsulation layer) in the wafer;
    Superimposing the ion-implanted silicon wafer on another silicon wafer such that the ion implanted surface closely contacts the other silicon wafer through the oxide film;
    Obtaining an SOI wafer by performing a heat treatment to peel off a portion of the ion-implanted wafer while using the microbubble layer as a peeling surface to form a thin film;
    It is made, including
    SOI wafer manufacturing method which removes the defect layer in the peeling surface of the SOI wafer thus obtained through vapor phase etching.
    [2" claim-type="Currently amended] Implanting hydrogen or rare gas ions into the top surface of the silicon wafer to form a microbubble layer (encapsulation layer) in the wafer;
    Superimposing the ion-implanted wafer on the insulator wafer such that the ion-implanted surface closely contacts the insulating wafer; And
    Performing a heat treatment to exfoliate a portion of the ion-implanted wafer, using the microbubble layer as the exfoliation surface to form a thin film;
    It is made, including
    SOI wafer manufacturing method of removing the defect layer of the peeling surface of the thus-obtained SOI wafer by vapor phase etching.
    [3" claim-type="Currently amended] The method of claim 1, wherein the defect layer is etched to a depth of 200 nm or more by vapor phase etching.
    [4" claim-type="Currently amended] 3. The method of claim 2 wherein the defect layer is etched to a depth of at least 200 nm by vapor phase etching.
    [5" claim-type="Currently amended] The method of claim 1, wherein the surface treated by vapor phase etching is further subjected to mirror polishing.
    [6" claim-type="Currently amended] The method of claim 2, wherein the surface treated by the vapor phase etching is further subjected to mirror polishing.
    [7" claim-type="Currently amended] 4. The method of claim 3, wherein the surface treated by vapor phase etching is further subjected to mirror polishing.
    [8" claim-type="Currently amended] The method of claim 4, wherein the surface treated by vapor phase etching is further subjected to mirror polishing.
    [9" claim-type="Currently amended] SOI wafer prepared according to the method of claim 1.
    [10" claim-type="Currently amended] SOI wafer prepared according to the method of claim 2.
    [11" claim-type="Currently amended] SOI wafer prepared according to the method of claim 3.
    [12" claim-type="Currently amended] SOI wafer prepared according to the method of claim 4.
    [13" claim-type="Currently amended] SOI wafer prepared according to the method of claim 5.
    [14" claim-type="Currently amended] SOI wafer prepared according to the method of claim 6.
    [15" claim-type="Currently amended] SOI wafer prepared according to the method of claim 7.
    [16" claim-type="Currently amended] SOI wafer prepared according to the method of claim 8.
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    同族专利:
    公开号 | 公开日
    US6140210A|2000-10-31|
    JP3324469B2|2002-09-17|
    JPH11102848A|1999-04-13|
    EP0905767A1|1999-03-31|
    KR100562437B1|2006-07-03|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-09-26|Priority to JP9-279878
    1997-09-26|Priority to JP27987897A
    1998-09-23|Application filed by 와다 다다시, 신에쯔 한도타이 컴파니 리미티드
    1999-04-26|Publication of KR19990030065A
    2006-07-03|Application granted
    2006-07-03|Publication of KR100562437B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP9-279878|1997-09-26|
    JP27987897A|JP3324469B2|1997-09-26|1997-09-26|Method for producing SOI wafer and SOI wafer produced by this method|
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